In order to improve, noise, jitter, duty cycle distortion, and skew in distribution of gigahertz clock signals in a clock tree, differential signals have been used. Specifically, U.S. Pat. No. 6,657,474, titled “Circuits for a Low Swing Clocking Scheme”, by H. D. Varadarajan, issued Dec. 2, 2003, in FIG. 3 discloses a translator/driver circuit that receives a full voltage swing clock signal from a phase locked loop and converts the clock signal to a low voltage swing clock signal. The translator/driver circuit has the disadvantage that several repeaters are necessary to amplify the signals along an interconnection line. In addition the translator/driver circuit as shown in FIG. 5 of the patent, if it works at all, has a gain that appears flat across frequency, hence not compensating for the high frequency attenuation of the interconnection line.
Therefore, there is a need for a better driver circuit that converts a full voltage swing clock signal input to produce a low voltage swing clock signal output, which can be driven over an interconnection line in an integrated circuit (IC).